VLSI CLUB
Become An ASIC engineer
VLSI CLUB trains the students in the following domains.
RTL design engineer
An RTL design engineer can design an ASIC using Verilog. The design will be Digital. They have the knowledge of creating memories,modelling in different clock domains. They can design combinational,synchronous and asynchronous sequential circuits. They working in real time application projects.
Backend design engineer
The Back-end designers can design an ASIC in the Back-end.Here the students learning the designs using cadence Virtuoso tools. The design the memories like SRAM, ADC,DAC and etc...
Verification engineer
Verification engineers verify the ASIC design and report the bugs if any. The most important part of a good working ASIC design is verification. Because here only the errors are found before a product is released. They will use some high level languages such as System Verilog, System c,UVM. In VLSi club the students will learn System Verilog as HVL(Hardware verification language).